The ADuCM320 is a fully integrated single package device that incorporates high performance analog peripherals together with digital peripherals controlled by an 80 MHz ARM? Cortex?-M3 processor and integral flash for code and data.
The ADC on the ADuCM320 provides 14-bit, 1 MSPS data acquisition on up to 16 input pins that can be programmed for single-ended or differential operation. The voltage at the IDAC output pins may also be measured by the ADC, which is useful for controlling the power consumption of the current DACs. Additionally, chip temperature and supply voltages can be measured.
The ADC input voltage is 0 V to VREF. A sequencer is provided, which allows a user to select a set of ADC channels to be measured in sequence without software involvement during the sequence. The sequence can optionally repeat automatically at a user selectable rate.
Up to eight VDACs are provided with output ranges that are programmable to one of two voltage ranges. The VDAC outputs have an enhanced feature of retaining their output voltages during a watchdog or software reset sequence.
Four IDAC sources are provided. The output currents are programmable with ranges of 0 mA to 150 mA. A low drift band gap reference and voltage comparator complete the analog input peripheral set.
The ADuCM320 has a low power ARM Cortex-M3 processor and a 32-bit RISC machine that offers up to 100 MIPS peak performance. Also integrated on chip are 2 × 128 kB Flash/EE memory and 32 kB of SRAM. The flash comprises of two separate 128 kB blocks supporting execution from one flash block and simultaneous writing/erasing of the other flash block.
The ADuCM320 operates from an on-chip oscillator or a 16 MHz external crystal and a PLL at 80 MHz. This clock can optionally be divided down to reduce current consumption. Additional low power modes can be set via software. In normal operating mode, the ADuCM320 digital core consumes about 300 μA per MHz. The device includes an MDIO interface capable of operating at up to 4 MHz. The capability to simultaneously execute from one flash block and write/erase the other flash block makes the ADuCM320 ideal for 10G, 40G, and 100G optical applications. User programming is eased by receiving interrupts after PHYADR, DEVADD, and end of frame, and by incorporating PHYADR and DEVADD hardware comparators. In addition, the nonerasable kernel code plus flags in user flash provide assistance by allowing user code to robustly switch between the two blocks of user flash code and data spaces, as required for MDIO.
The ADuCM320 integrates a range of on-chip peripherals that can be configured under software control, as required in the application. These peripherals include 1 × UART, 2 × I2C, and 2 × SPI serial I/O communication controllers, GPIO, 32-element programmable logic array, 3 general-purpose timers, plus a wake-up timer and system watchdog timer. A 16-bit PWM with seven output channels is also provided.
GPIO pins on the device power up in input mode with an internal pull-up resistor. In output mode, the software chooses between open-drain mode and push-pull mode. The outputs can drive at least 4 mA. The pull-up resistors can be disabled and enabled in software. In GPIO mode, the inputs can be enabled to monitor the pins. The GPIO pins can also be programmed to handle digital or analog peripheral signals, in which case the pin characteristics are matched to the specific requirement.
A large support ecosystem is available for the ARM Cortex-M3 processor to ease product development of the ADuCM320. Access is via the ARM serial wire debug port (SW-DP). On-chip factory firmware supports in-circuit serial download via MDIO.